Daidalos develops modular AI accelerator IP that uses an algorithm-mapping architecture to reorganize hardware around how AI data moves, enabling more efficient AI execution with lower power consumption and implementation requirements.
50%
Of total energy system demand is because of AI workloads, while chip design cycles can take up to 36 months and one month of delay can cost up to $30M in lost revenue. Edge and real-time applications often require end-to-end latency below 10 ms.
AI acceleration has become a mandatory component of modern chip architectures, but conventional approaches can require significant power and hardware resources. At the same time, lengthy chip development cycles create significant costs and delays for chipmakers.
Daidalos analyzes an AI algorithm, understands how its data needs to move and reorganizes the hardware around that data flow. Its AI accelerator is an integrable hardware module designed to execute AI efficiently, with a business model based on semiconductor IP licenses and royalties.
1.45×
performance (400 vs. 275 TOPS/s) compared with NVIDIA Jetson Orin, 4× efficiency (38 vs. 11 TOPS/W), and 6× smaller area (30 mm² vs. 200 mm²).
By optimizing data movement and computation at the architectural level, Daidalos reduces the energy required for AI workloads while achieving higher computational performance in a smaller hardware footprint.
1.45× performance, 4× energy efficiency and 6× smaller area compared with NVIDIA Jetson Orin. Daidalos also offers IP licensing and royalties rather than requiring customers to manufacture a complete chip themselves.

Sandbox Program
Batch #13
HQ Country
Italy
Sector
AI Hardware & Semiconductors
Type of Solution
Hardware

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